hsmp-383x surface mount rf pin diodes data sheet features ? diodes optimized for: low capacitance switching low current attenuator ? surface mount sot-23 package single and dual versions tape and reel options available ? low failure in time (fit) rate [1] ? lead-free note: 1. for more information see the surface mount pin reliability data sheet. package lead code identifcation (top view) description/applications the hsmp-383x series of general purpose pin diodes are designed for two classes of applications. the frst is attenuators where current consumption is the most important design consideration. the second application for this series of diodes is in switches where low capacitance is the driving issue for the designer. the hsmp-386x series total capacitance (c t ) and total resistance (r t ) are typical specifcations. for applications that require guaranteed performance, the general purpose hsmp-383x series is recommended. a spice model is not available for pin diodes as spice does not provide for a key pin diode characteristic, carrier lifetime. common cathode #4 common anode #3 series #2 single #0
2 absolute maximum ratings [1] t c = 25c symbol parameter units absolute maximum i f forward current (1 ms pulse) amp 1 p t total device dissipation mw [2] 250 p iv peak inverse voltage same as v br t j junction temperature c 150 t stg storage temperature c -65 to 150 notes: 1. operation in excess of any one of these conditions may result in permanent damage to this device. 2. cw power dissipation at t lead = 25c. derate to zero at maximum rated temperature. pin general purpose diodes, electrical specifcations t c = 25c minimum maximum maximum part package breakdown series total number marking lead voltage resistance capacitance hsmp- code code confguration v br (v) r s () c t (pf) 3830 k0 0 single 200 1.5 0.3 3832 k2 2 series 3833 k3 3 common anode 3834 k4 4 common cathode test conditions v r = v br i f = 100 ma v r = 50 v measure f = 100 mhz f = 1 mhz i r 10 m a typical parameters at t c = 25c part number series resistance carrier lifetime reverse recovery time total capacitance hsmp- r s () (ns) t rr (ns) c t (pf) 383x 20 500 80 0.20 @ 50 v test conditions i f = 1 ma i f = 50 ma v r = 10 v f = 100 mhz i r = 250 ma i f = 20 ma 90% recovery
3 typical parameters at t c = 25c (unless otherwise noted), single diode figure 2. rf capacitance vs . rev erse bias . 0.15 0.30 0.25 0.20 0.35 0 2 6 4 1 0 1 2 8 1 6 14 18 20 tot al cap a cit ance (pf) reverse vo lt ag e (v) 1 ghz 100 mhz 1 mhz 120 110 100 90 80 70 60 50 40 1000 100 10 diode mounted as a series attenuator in a 50 ohm micr ostrip and t ested at 123 mhz diode rf resist ance () figure 4. 2nd harmonic input intercept p oint vs . diode rf resistance for attenuators . input intercept point (dbm ) 120 115 110 105 100 95 90 85 1 1 0 3 0 i f ? for w ard bias current (ma) figure 5. 2nd harmonic input intercept p oint vs . fo rw ard bias current for switches . input intercept point (dbm ) diode mounted as a series attenuator in a 50 ohm micr ostrip and t ested at 123 mhz 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 i f ? for w ard current (ma) v f ? for w ard vo lt ag e (ma) figure 1. fo rw ard current vs . fo rw ard v oltage . 125c 25c ?50c 1000 100 10 10 20 30 t rr - reverse recovery time (ns) forward current (ma) figure 6. reverse recovery time vs. forward current for various reverse voltage. hsmp-3830 v r = 5v v r = 10v v r = 20v figure 3. rf resistance at 25c vs. forward bias current. 1000 100 10 1 0.1 rf resistance (ohms) i f ? forward bias current (ma) 0.01 0.1 1 1 0 100
4 typical applications for multiple diode products figure 7. simple spdt switch, using only positive current. figure 8. high isolation spdt switch, dual bias. figure 9. switch using both positive and negative current. figure 10. very high isolation spdt switch, dual bias. rf common rf 1 bias 1 rf 2 bias 2 rf common bias bias rf 2 rf 1 rf common rf 1 rf 2 bias rf common rf 2 rf 1 bias
5 typical applications for multiple diode products (continued) input rf in/out figure 11. four diode attenuator . see an1048 for details . fixed bias vo lt ag e v ariable bias figure 12. high isolation spst switch (repeat cells as required). bias
6 ordering information specify part number followed by option. for example: hsmp - 383x - xxx bulk or tape and reel option part number surface mount pin diode package dimensions outline 23 (sot-23) recommended pcb pad layout for avagos sot - 23 products package characteristics lead material ............................................................................................................................. alloy 42 lead finish .......................................................................................... tin 100% (lead-free option) maximum soldering temperature ............................................................. 260c for 5 seconds minimum lead strength ............................................................................................ 2 pounds pull typical package inductance ....................................................................................................... 2 nh typical package capacitance ............................................................... 0.08 pf (opposite leads) profle option descriptions -blkg = bulk -tr1g = 3k pc. tape and reel, device orientation; see figure 13 -tr2g = 10k pc. tape and reel, device orientation; see figure 13 tape and reeling conforms to electronic industries rs-481, taping of surface mounted components for automated placement. e b e 2 e 1 e 1 c e x x x l d a a 1 n o t e s : x x x - p a c k a g e m a r k i n g d r a w i n g s a r e n o t t o s c a l e d i m e n s i o n s ( m m ) m i n . 0 . 7 9 0 . 0 0 0 0 . 3 0 0 . 0 8 2 . 7 3 1 . 1 5 0 . 8 9 1 . 7 8 0 . 4 5 2 . 1 0 0 . 4 5 m a x . 1 . 2 0 0 . 1 0 0 0 . 5 4 0 . 2 0 3 . 1 3 1 . 5 0 1 . 0 2 2 . 0 4 0 . 6 0 2 . 7 0 0 . 6 9 s y m b o l a a 1 b c d e 1 e e 1 e 2 e l 0 . 0 3 9 1 0 . 0 3 9 1 0 . 0 7 9 2 . 0 0 . 0 3 1 0 . 8 d i m e n s i o n s i n i n c h e s m m 0 . 0 3 5 0 . 9
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies. all rights reserved. obsoletes 5989-4027en av02-1425en - june 2, 2009 figure 13. options -tr1, -tr2 for sot-23 packages. tape dimensions and product orientation for outline sot-23 note: "ab" represents package marking code . "c" represents date code. end vie w 8 mm 4 mm top view abc abc abc abc device orientation for outlines sot-23 user feed direction cover tape carrier tape reel 9 max a 0 p p 0 d p 2 e f w d 1 ko 8 max b 0 13.5 max t1 descriptio n s ymbol size (mm) size (inches) lengt h widt h depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.15 0.10 2.77 0.10 1.22 0.10 4.00 0.10 1.0 0 + 0 .05 0.124 0.004 0.109 0.004 0.048 0.004 0.157 0.004 0.039 0.002 cavity diameter pitch positio n d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforatio n widt h thickness w t1 8.00 + 0.30 ? 0.10 0.229 0.013 0.315 + 0.012 ? 0.004 0.009 0.0005 carrier tape cavity to perforatio n (width direction ) cavity to perforatio n (length direction ) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distanc e between centerlin e
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